Expanded multi-stage time connection network

ABSTRACT

Time connection network consisting of two identical networks, each input switch of a network being connected to the intermediate switches, each intermediate switch comprising two assemblies consisting of input registers and a buffer memory, each assembly being connected to a control memory and to the same output registers.

O United States Patent 1151 3,674,938 Jacob July 4, 1972 [54] EXPANDED MULTI-STAGE TIME [56] References Cited CONNECTION NETWORK UNITED STATES PATENTS [72] Perms 3,461,242 8/1969 lnose et al ..179/15 AQ 3,492,430 1/1970 Vigliante ..|79/15 AT [73] Assignees: C.l.T.-Compagnie lndustrielle Des Telecommunications, Paris, France; Societe m y i e o ld J. Y usko Lannionaise D'Electronique, Lannion, yg. Antone"! & France T B R [22] Filed: Dec. 29,1970 i k ST AC f l ime connection networ consisting 0 two identica net- PP 102,371 works, each input switch of a network being connected to the intermediate switches, each intermediate switch comprising [30] Foreign Applicafinn priority Dam two assemblies consisting of input registers and a buffer memory, each assembly being connected to a control memory Dec. 29, France 1 9 and to the ame output registers [52] US. Cl. ..179/l5 AQ, 340/166 R 8 Claims, 2 Drawing Figures [51] Int. Cl. ..H04j 3/08, H04q 3/42 1 [58] FieldofSearch ..l79/l5 AQ,15 AT, 18 J; 340/166 EXPANDED MULTI-STAGE TIME CONNECTION NETWORK The present invention relates to a large-capacity time connection network usable particularly in automatic telephone switching, and more generally in the industries of telecommunications, telecontrol, telesignalling, etc.

Known in the art are non-blocking time connection networks, such as the network disclosed in my copending US. Pat. application No. 39,786, filed May 22, 1970, including time switches with n incoming network lines and m outgoing network lines, each network line containing x time channels of y binary elements, for example, 32 time channels of 8 binary elements. Also known from the aforementioned patent application is a time connection network comprising three stages, namely, one input stage, one intermediate stage, and one output stage, and this network has n incoming time network lines, and n outgoing time network lines allowing for the connection or linkage between any one time channel of the n input network lines and any one time channel of the n output network lines; and the trafiic may be assured either without blocking or with blocking, according to the number m of the circuit breakers provided in the intermediate stage.

It is thus possible to obtain, with a connection network having three stages, a network of 32 X 1024 incoming and outgoing network lines, thereby allowing for the access of 1024 X 32 circuits, or about 32,000 circuits. In the case of a nonblocking arrangement, such a system provides for the installation of 16,000 complete conversation circuits. In order to obtain a network comprising more than 32,000 circuits, it is only necessary to increase the number of stages of the network to five stages, which then gives a possibility of handling n network lines, or about 1 million circuits. It is readily conceivable that a network of such capacity is not practical and the cost thereof is ill justified when one merely wants to double the capacity of a network having a 32,000 circuit capacity, since a network with n lines, or five stages, has a greatly higher per circuit cost than a network with three stages.

The present invention is directed to and concerned with the extension of the capacity of a connection network having n lines, making it possible to obviate the disadvantages and drawbacks pertaining to the cost and the complexity of expanding such a networkinto a connection network with n network lines. More particularly, it envisages doubling the capacity of the network having n network lines.

The present invention relates to a time connection network comprising an input stage, an intermediate stage and an output stage, each stage consisting of a certain number of time switches, characterized by the fact that it consists of first and second networks which are identical to each other and each have n incoming network lines and n outgoing network lines, each intermediate switch of the first and of the second networks having a double number of input registers and buffer memories, and the control memory comprising an additional binary element per word. Each output register of an input switch of one network is also connected to the corresponding additional input register of the corresponding intermediate switch of the other network, the additional input registers of one intermediate switch being connected to the additional buffer memory of the aforementioned intermediate switch, and the aforementioned memory being connected to the control memory as well as to the output registers of the intermediate switch.

The characteristics of the connection network as proposed by the present invention will be better understood orrthe basis of the following detailed description of one embodiment thereof, given solely for purposes of example, and with the aid of the accompanying drawings, wherein:

FIG. 1 is a schematic representation of a time connection network having three stages, according to the present invention; and

FIG. 2 illustrates schematically a time connection network as proposed by the present invention, showing the principal constituents of the time switches.

FIG. 1 is a schematic diagram of a connection network R having three stages and two n network lines consisting of two networks R, and R with n network lines each, and consisting of one input stage EE, one intermediate stage El, and one output stage ES.

The input stage of the network R, comprises n switches C,E, to C,E,; the input stage of the network R, comprises n switches C,E, to C,E,. The intermediate stage of the network R, comprises n principal switches C,I, to C,I, and n auxiliary switches C,I', to C,l,,, these switches having the same outputs as those of the corresponding principal circuit breakers. The intermediate stage of the network R comprises n principal switches C 1, to C l, and n auxiliary switches C 1, to C,I these switches having the same outputs as those of the corresponding principal switches. The output stage of the network R, comprises n switches C,S, to C,S,,; the output stage of the network R comprises it switches C 8, to C 8 The outputs of the input switches of the network R, are connected to the inputs of the principal intermediate switches of the network R, as well as to the inputs of the auxiliary intermediate switches of the network R just as the outputs of the input switches of the network R are connected to the inputs of the principal intermediate switches of the network R as well as to the inputs of the auxiliary intermediate switches of the network R,. In a general fashion, the connections or linkages between the output registers of C,E, to C,E,, with respect to the input registers of switches C,I, to C,I,, are as disclosed in my copending application referred to hereinabove; and the same holds true for the connections or linkages between switches C,E, to C,E,, and C 1, to C l',,, for the connections between C,E, to C,I,, to with C to C,I, and for the connections between C,E, to C,E,, with C,I', to C,l',,. The connections between the intermediate switches and the output switches do not pose any problem; the outgoing network lines of the switches C,I, to C,I,, and C l, to C,I,, are common to the auxiliary switches C, I, to C,I and C l', to C I',,, and the linkages or connections are made in accordance with the aforementioned patent application.

In this example, all of the switches have a square configuration; they each have n inputs and n outputs. But the present invention is not limited to this single case and is applicable in a general fashion to any network whose p input switches have n incoming network lines and m outgoing network lines, which necessitates the use of m intermediate switches having p incoming lines and p outgoing lines; the output switches being p in number having m incoming lines and n outgoing lines.

FIG. 2 shows by way of example, and without being limiting, three time switches of a connection network R with three stages, such as shown in FIG. 1 and showing the detailed configuration thereof. It is assumed that each time switch, whether it be an input switch such as CE,, an output switch such as C,-S,, or an intermediate switch such as C,l, or Cll',, comprises 32 incoming network lines and 32 outgoing network lines; accordingly, square switches are thus involved here.

Disposed in the input switch C,E, are 32 input registers REE,, REE, REE, in which temiinate respectively the input network lines LRE,, LRE, LRE,,. A buffer memory MTE, is also provided consisting of 32 blocks or elementary memories each comprising 32 words of eight binary elements; the elementary memories are addressable memories, and it will be assumed in accordance with the invention that static addressable memories are involved here. A control memory MCE, is provided comprising 1,024 words like the buffer memory, but having l0 binary elements and allowing for addressing one word among 1,024. These 1,024 words also constitute 32 blocks of 32 words, one block being associated with one output register. The control memories may be of two types, namely, either addressable or with circulation word per word (parallel series memory of 1,024 words of ten binary elements). Thirty-two output registers RSE,, RSE, RSE,,, are provided from which extend thirty-two intermediate network lines LREI,, LREI, LREl respectively toward the corresponding input registers ofthe intermediate switches C, I, to C,I and switches C 1, to C 1 32 of the intermediate stage. These connections or linkages between the output registers of switch C,E, and the input registers of switches C,I, to Q1 and C I', to C l' are made in accordance with the aforementioned patent application.

In a manner similar to the input switch C,E,, one finds on the switches C,I, and C,S, analogous elements; thus, the input registers REE, to REE,,- are respectively replaced by the registrs REI, to REI for the switch CI, and RBI, to REI for C,I, and by the registers RES, to RES for the switches C,S,; likewise, the buffer memory MTE is replaced by the buffer memory MTI, for the switch C,I, and MTI', for C,I', and by the buffer memory MTS, for the switch C,S, etc., and an identical structure is found in each of the switches C,E,, C,l, and C,S,.

In addition to this identical structure, one finds in the intermediate switch C,I,, in addition to the input registers RBI, to REI which are identical to the other registers, a buffer memory MTI', which is associated with these registers and depends like the buffer memory MTl, upon the control memory MCI, to which there has been added one additional binary element per word, or for a memory of 1,024 words 1,024 additional binary elements designated as E.B., each additional binary element making it possible to determine to which buffer memory, MTI, or MTI1,, the marked or registered word is associated.

There is also found, starting from each output register of the input switch, one incoming network line for one intermediate switch of the network R of FIG. 1; thus, from the register RSE, originates a network line LR,EI', terminating at the first input register of the intermediate switch C I',; likewise from the register RSE,,, there originates a network line LR,EI,,. terminating at the 32 input register of the intermediate switch C I In addition, the input register REI, of the intermediate switch C,l', is connected by means of the network line LR El, of the intermediate switch C,I',, the input register REI' being linked to the first register of the switch C E,,.

The principle of establishing a connection between an incoming network line and an outgoing network line in a time connection network with stages such as R, or R in FIG. 1 has been described in the aforementioned patent application. The principal of establishing a connection between an incoming network line of the network R and an outgoing network line of the network R, in a time connection network with R stages according to the present invention, as shown in FIG. 1, is as follows.

It is assumed that the choice of the incoming network line and of the outgoing network line is made by means of members outside of the network, in practice such marking of a selected input and selected output is performed by means of selection units. The number of the time channel of the incoming network line and the number of the time channel of the outgoing network line are also assumed to be chosen by the selection units.

If one considers first of all a time switch such as C,E, (FIG. 2) for purposes of establishing a connection between a time channel ti of an input register, for example, REE,, and a time channel tj of an output register, for example RSE,, it sufiices to write in a word of be in the control memory MCE associated with the time channel tj of the output register RSE,, the address of the word of the buffer memory MT E, associated with the time channel ti of the input register REE,. In fact, there are associated with each input register of a circuit breaker 32 words of the buffer memory corresponding to the 32 time channels, and associated with each output register are 32 words of the control memory. In this fashion, the address written in the control memory makes it possible to read in the buffer memory the information emitted at the input and for transferring it into the output register, and thus for establishing a time connection. If one now considers a connection network with three stages such as shown in FIG. 1, a connection between a time input channel of the network R and a time output channel of the network R, is established with the aid of three connections: one connection in an input switch; one connection in an intermediate switch, and one connection in an output switch. It is obviously necessary that the output of the input switch whose output must intum correspond to the input of the output switch.

A numerical example of a connection through a network with three stages will be given with reference to FIGS. 1 and 2.

It is assumed that the input of the connection network consists of the time channel t,,, of the network line LRE, of the input switch CE, and that the output of the connection network consists of the time channel t,,, of the network line LRS of the output switch C C,S,.

The intermediate switch C,I, is utilized and in this switch a time channel of the input register RBI, and a time channel or path of the output register RSI, is used, for example, the time channels I and t respectively. It follows that the time channels t of the register RSE, of the switch C E, and 28 of the register RES, of the switch C,S, will also be utilized.

The complete connection is made by recording or storing certain data. In the switch C 5,, there is recorded in the control memory MCE, and in word No. 15 of the block of 32 words associated with RSE, the address of word No. 10 of the block of 32 bufier words associated with REE,. In the switch C,I',,,, there is recorded in the control memory MCI, and in word No. 28 of the block of 32 words associated with RSI of the address of word No. 15 the block of 32 buffer words associated with R51, as well as in be of the address of the bufl'er memory MTI', associated with REI',, that is to say, to position at 1" the additional b.e. of word No. 28 of the block of 32 words associated with RSI, and in MCI,. In the output switch C,S,, there is recorded in the control memory MCS, and in word No. 18 (1, of the block of 32 words associated with RS8 the address of word No. 28 of the block of 32 buffer words associated with RES,.

It will be noted that, since there takes place in a time switch the transfer from an input toward the output connected to each sampling period T, three periods T will be required to transfer an infonnation from an input to an output of a time network having three stages.

The installation of a telephone time communication necessitates two connections through a connection network, namely, one from the subscribing caller to the subscriber being called, and the other from the subscriber being called toward the subscribing caller. These two connections are obviously not independent from each other; as a matter of fact, since the subscriber modulation equipment is sampled at the same time emission side" and receiving side, the coded signal to be emitted by a subscriber toward his correspondent and the coded signal to be received by the correspondent must be present at the same time in the modulation equipment of the subscriber. Hence, the number of the sampling time channel of a subscribing caller determines the time channel number on the incoming network line (LRE) of the caller connection toward the person being called as well as the time channel number on the outgoing network line (LRS) of the connection from the person called toward the person calling. It is understood that, if the delays of transmission between the connection network and the subscriber modulation equipment were nil, the two time channels would have the same number, and this is what has been assumed in the numerical example which will be given hereinbelow; in fact, there is a constant difference between the time channel on LRE and the time channel on LRS in the two directions of the connection in a manner such that, when one of the time channels is known, the other is readily deduced therefrom by either addition or subtraction of a constant.

The numerical example given hereinabove concerning the connection through a connection network having three stages corresponds to the connection of caller toward the person called; this example will be completed by the connection from a person called to the caller. This latter connection will be established between the time channel I of LRE (FIG. 1) of the switch C li'l and the time channel 2 of LRS of the switch C 8,. The intermediate switch C 1 will be utilized and in this switch the time channel r of R131 and the time channel r of RSI, for example, by assuming that these time channels be not occupied (these time channels will be shown encircled in FIGS. 1 and 2).

The connection is made by recording or storing data as indicated hereinafter. in the switch C 1,, there is recorded in the control memory MCE, and in word No. 12 of the block of 32 words associated with RSE,, the address of word No. 18 of the block of 32 buffer words associated with REE-. In the switch C l' there is recorded in the control memory MCI. and in word No. 13 of the block of 32 words associated with RSL, the address of word No. 12 of the block of 32 buffer words associated with REI',, as well as in b.e. of the address of the buffer memory MT! associated with REI',. In the switch C 8,, there is recorded in the control memory MCS and in word No. 10 of the block of 32 words associated with RSS,, the address of word No. 13 of the block of 32 buffer words associated with RES It is understood that the operation asdescribed hereinabove which allows for connecting a subscribing caller of the network R (FIG. 1) to a subscriber being called in network R may be easily transposed if the subscribing caller should belong to network R and the subscriber being called belongs to network R In a network comprising stages such as described above, the fact that it is possible to send sounds or signals at voice frequencies brings into play only the output switches CS. It is assumed that the number of signals and sounds is smaller than 32 and that these signals are available in the form of coded modulation in the form of impulses (MCI), such as speech signals, at the input of the connection network, and that they are furnished by a member outside of the network. Each output switch CS will then dispose of a 33 incoming network line, that is to say, of a 33 register RES and a 33 buffer memory block of 32 words in which there are recorded at each sampling period successive and periodic codes of the 32 signals at vocal frequencies.

in order to send a sound or signal j to a subscriber being connected to an output register RSS, during a time channel ti, it will be sufficient to inscribe or record in the control memory of the switch at the word No. i of the block No. n of the 32 words being associated with the resister RS8, the number of j of the buffer memory word that is affected or influenced at this sound in the block of the 32 words associated with the register RES It is understood that the present invention is by no means v limited to the embodiment thereof which has been described and shown herein, which has been given solely by way of example. More particularly, it is possible to modify certain provisions thereof or to exchange certain means for equivalent means without departing from the spirit and scope of the present invention.

What is claimed is:

l. A time division multiplex connection system comprising at least a pair of stage networks each including at least one input stage, an intermediate stage and an output stage, each stage being formed of a certain number of time switches each having a certain number of incoming network lines and a certain number of outgoing network lines, time division multiplex connections between the outgoing lines of said input stage and the incoming lines of said intermediate stage and between the outgoing lines of said intermediate stage and the incoming lines of said output stage, each incoming line and each outgoing line comprising several time channels and each time channel comprising several time slots, each time switch of an input stage of one network being connected also to the incoming lines of the intermediate stage of the other network so that any one time channel of any one input switch can be connected to any one time channel of any one output switch in either network.

. output means applying said several 2. A time division multiplex connection system as defined in claim 1, wherein each switch is composed of input means receiving said several time channels on said incoming lines,

time channels on said outgoing lines and memory means for transferring said time channels from said input means to said output means.

3. A time division multiplex connection system as defined in claim 2, wherein said memory means includes control means for transferring a given time channel on one input line to a different time channel on an output line of the associated switch.

4. A time division multiplex connection system as defined in claim 2, wherein each network comprises only three stages, an input stage comprising p input switches with n inputs and m outputs, an intermediate stage comprising two m intermediate switches with p inputs and q outputs, an output stage comprising q output switches with m inputs and n outputs, each input switch receiving n incoming network lines with x time channels and its m outputs being connected in parallel to respective inputs of m intermediate switches in each network, each output switch having n outgoing network lines with .1: time channels, the m inputs of each output switch being connected to the outputs of the m intermediate switches, the p inputs and q outputs of each intermediate switch being thus respectively connected to the p input switches and the q output switches so that each network thus determined comprises n incoming lines and n outgoing lines, whereby a connection is possible between any time channel of the n outgoing network lines and any time channel of the n outgoing network lines, the traflic being provided without blocking or with blocking depending on the number m of switches of the intermediate stage.

5. A time division multiplex connection system according to claim 4, wherein the intermediate switches comprise the same number of inputs and outputs (p q), the connection system being thus symmetrical.

6. A time division multiplex connection system according to claim 2, with each network comprising three stages, the input stage comprising 11 switches with n inputs and (Zn 1) outputs, the intermediate stage comprising 2(2n-l switches with n inputs and n outputs and the output stage comprising n switches with (Zn-1) inputs and n outputs, some of said time division multiplex connections existing between the (Zn 1) outputs of each input switch and the inputs of (Zn l) intermediate switches in each network and other of said time division multiplex connections existing between the (Zn l) inputs of each output switch and (2n-l) intermediate switches in each network so as to form a time connection network without blocking having n incoming network lines and n network lines.

7. A time division multiplex connection system according to claim 1, wherein each time switch at least comprises a plurality of input registers equal in number to the number of incoming network lines to the switch, a plurality of output registers equal in number to the outgoing network lines from the switch, each incoming and outgoing network line comprising 32 time channels, a buffer memory operatively associated with the incoming network lines and constituted by as many addressable memory blocks as there are incoming network lines to store data therefrom, each block comprising 32 words of y bits corresponding to 32 time channels, a control memory operatively associated with the outgoing network lines and constituted by as many memory blocks as there are outgoing network lines, each block comprising 32 words of z bits corresponding to the 32 time channels so that the establishment of a connection between a time channel ii of an input register and a time channel of an output register is effected by means in said control memory writing in the work of 2 control memory bits associated with the time channel U of the output register allocated to the nth outgoing network line the address of the buffer memory word associated with the time channel ti of the input register allgcatedtothe r r z th incoming network line, and wherein each intermediate stage switch further includes a second group of input registers equal in number to the number of incoming lines from the input stage of one network and a second group of addressable memory blocks in said buffer memory thereof corresponding to said second group of input registers, said control memory in each intermediate stage switch having a storage facility for an additional binary element per address word serving to switch said address of one of said second group of input registers.

8. A time division multiplex connection system as defined in claim 1, wherein each time switch comprises a plurality of input regisers equal in number to the number of incoming network lines to the switch, a plurality of output registers equal in number to the outgoing network lines from the switch, a bufier memory including an individual memory portion for each input register having a plurality of time channels equal in number to the time channels provided by each incoming network line, a control memory having an addressable memory block corresponding to each output register, each memory block having a plurality of time channels equal in number to 8 the time channels provided by each outgoing network line, said control memory including means for transferring data in one time channel in said buffer memory to a different time channel of one of said outgoing network lines in accordance with the address of the input register and time channel thereof stored in the memory block corresponding to the required output register and the time channel of the memory block corresponding to the time channel of the outgoing network line to be used, and wherein each intermediate stage switch further includes a second group of input registers equal in number to the number of incoming lines from the input stage of one network and a second group of addressable memory blocks in said buffer memory thereof corresponding to said second group of input registers, said control memory in each intermediate stage switch having a storage facility for an additional binary element per address word serving to switch said address of one of said second group of input registers. 

1. A time division multiplex connection system compRising at least a pair of stage networks each including at least one input stage, an intermediate stage and an output stage, each stage being formed of a certain number of time switches each having a certain number of incoming network lines and a certain number of outgoing network lines, time division multiplex connections between the outgoing lines of said input stage and the incoming lines of said intermediate stage and between the outgoing lines of said intermediate stage and the incoming lines of said output stage, each incoming line and each outgoing line comprising several time channels and each time channel comprising several time slots, each time switch of an input stage of one network being connected also to the incoming lines of the intermediate stage of the other network so that any one time channel of any one input switch can be connected to any one time channel of any one output switch in either network.
 2. A time division multiplex connection system as defined in claim 1, wherein each switch is composed of input means receiving said several time channels on said incoming lines, output means applying said several time channels on said outgoing lines and memory means for transferring said time channels from said input means to said output means.
 3. A time division multiplex connection system as defined in claim 2, wherein said memory means includes control means for transferring a given time channel on one input line to a different time channel on an output line of the associated switch.
 4. A time division multiplex connection system as defined in claim 2, wherein each network comprises only three stages, an input stage comprising p input switches with n inputs and m outputs, an intermediate stage comprising two m intermediate switches with p inputs and q outputs, an output stage comprising q output switches with m inputs and n outputs, each input switch receiving n incoming network lines with x time channels and its m outputs being connected in parallel to respective inputs of m intermediate switches in each network, each output switch having n outgoing network lines with x time channels, the m inputs of each output switch being connected to the outputs of the m intermediate switches, the p inputs and q outputs of each intermediate switch being thus respectively connected to the p input switches and the q output switches so that each network thus determined comprises n2 incoming lines and n2 outgoing lines, whereby a connection is possible between any time channel of the n2 outgoing network lines and any time channel of the n2 outgoing network lines, the traffic being provided without blocking or with blocking depending on the number m of switches of the intermediate stage.
 5. A time division multiplex connection system according to claim 4, wherein the intermediate switches comprise the same number of inputs and outputs (p q), the connection system being thus symmetrical.
 6. A time division multiplex connection system according to claim 2, with each network comprising three stages, the input stage comprising n switches with n inputs and (2n - 1) outputs, the intermediate stage comprising 2(2n- 1) switches with n inputs and n outputs and the output stage comprising n switches with (2n- 1) inputs and n outputs, some of said time division multiplex connections existing between the (2n - 1) outputs of each input switch and the inputs of (2n - 1) intermediate switches in each network and other of said time division multiplex connections existing between the (2n - 1) inputs of each output switch and (2n- 1) intermediate switches in each network so as to form a time connection network without blocking having n2 incoming nEtwork lines and n2 network lines.
 7. A time division multiplex connection system according to claim 1, wherein each time switch at least comprises a plurality of input registers equal in number to the number of incoming network lines to the switch, a plurality of output registers equal in number to the outgoing network lines from the switch, each incoming and outgoing network line comprising 32 time channels, a buffer memory operatively associated with the incoming network lines and constituted by as many addressable memory blocks as there are incoming network lines to store data therefrom, each block comprising 32 words of y bits corresponding to 32 time channels, a control memory operatively associated with the outgoing network lines and constituted by as many memory blocks as there are outgoing network lines, each block comprising 32 words of z bits corresponding to the 32 time channels so that the establishment of a connection between a time channel ti of an input register and a time channel of an output register is effected by means in said control memory writing in the work of z control memory bits associated with the time channel tj of the output register allocated to the nth outgoing network line the address of the buffer memory word associated with the time channel ti of the input register allocated to the mth incoming network line, and wherein each intermediate stage switch further includes a second group of input registers equal in number to the number of incoming lines from the input stage of one network and a second group of addressable memory blocks in said buffer memory thereof corresponding to said second group of input registers, said control memory in each intermediate stage switch having a storage facility for an additional binary element per address word serving to switch said address of one of said second group of input registers.
 8. A time division multiplex connection system as defined in claim 1, wherein each time switch comprises a plurality of input regisers equal in number to the number of incoming network lines to the switch, a plurality of output registers equal in number to the outgoing network lines from the switch, a buffer memory including an individual memory portion for each input register having a plurality of time channels equal in number to the time channels provided by each incoming network line, a control memory having an addressable memory block corresponding to each output register, each memory block having a plurality of time channels equal in number to the time channels provided by each outgoing network line, said control memory including means for transferring data in one time channel in said buffer memory to a different time channel of one of said outgoing network lines in accordance with the address of the input register and time channel thereof stored in the memory block corresponding to the required output register and the time channel of the memory block corresponding to the time channel of the outgoing network line to be used, and wherein each intermediate stage switch further includes a second group of input registers equal in number to the number of incoming lines from the input stage of one network and a second group of addressable memory blocks in said buffer memory thereof corresponding to said second group of input registers, said control memory in each intermediate stage switch having a storage facility for an additional binary element per address word serving to switch said address of one of said second group of input registers. 